1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and, more particularly, to an improvement of an insulated gate bipolar transistor and a power MOSFET having an insulated gate, which realizes a low gate capacity and a low short-circuit current at a low resistance, and to a method of manufacturing the insulated gate bipolar transistor.
2. Description of the Prior Art
In general power electronics for driving a motor and the like, power semiconductor elements of, for example, an insulated gate bipolar transistor (to be referred to as xe2x80x9cIGBTxe2x80x9d hereinafter) are mainly used as switching elements because of their characteristics in a region having a rated voltage of 300 V or more. Of these power semiconductor elements, there attract increasing attentions to an insulated gate semiconductor device having a trench gate, i.e., an insulated gate semiconductor device having a structure in which a gate electrode is buried in a trench formed in one major surface of a semiconductor substrate because of the following advantages. That is, the insulated gate semiconductor device can be easily micropatterned and integrated at a high density.
FIG. 6 is a sectional view showing an example of a structure of a conventional trench gate IGBT (to be referred to as xe2x80x9cTIGBTxe2x80x9d hereinafter) An example of a typical TIGBT configuration is shown in FIG. 7A as an upper plan view thereof, and in FIGS. 7B and 7C as sectional views taken on lines A-Axe2x80x2 and B-Bxe2x80x2 in FIG. 7A, respectively. The structure and operation of the conventional TIGBT will be briefly described below with reference to FIG. 6 and FIGS. 7A to 7C.
In the illustrated configuration, an n+-type buffer layer 102 is formed on a p+-type substrate 101, and a collector electrode 112 is formed on the lower surface of the p+-type substrate 101. An nxe2x88x92-type semiconductor layer (referred to as xe2x80x9cbase layerxe2x80x9d) 103 is formed on the n+-type buffer layer 102. Furthermore, in a cell region of the TIGBT, a p-type base region 104 is selectively formed by diffusing a p-type impurity on the upper surface of the nxe2x88x92-type base layer 103. In a part or the entire area of the upper surface of the p-type base region 104, an n+-type emitter region 105 is formed by selectively diffusing a high concentrated n-type impurity.
In this conventional configuration, a plurality of trenches 107 are formed to extend to cross the n+-type emitter region 105, and are arranged at predetermined intervals (i.e., pitches) W in parallel to each other. Each trench is formed to have such a depth that the trench extends from the level of the n+-type emitter region 105 to the nxe2x88x92-type base layer 103. A trench gate electrode 110 (110a, 110b and 110c) of the MOS transistor is buried in each of the trenches 107 through a gate insulating film 108. The p-type base region 104 opposing the gate electrode 110 and interposed between the n+-type emitter region 105 and the nxe2x88x92-type base layer 103 functions as a channel region.
The upper surface of the trench gate electrode 110 and a part of the upper surface of the n+-type emitter region 105 are coated with an insulating interlayer 109, and an emitter electrode 111 is formed to cover a part of the upper surface of the n+-type emitter region 105 and the entire upper surface of the insulating interlayer 109. Also, as shown in FIG. 6, a p-type semiconductor layer 113 for keeping a withstand voltage high is formed in a region immediately below a gate wiring layer GL.
FIGS. 8A, 8B, and 8C show a typical structure of a conventional carrier stored trench-gate bipolar transistor (to be referred to as xe2x80x9cCSTBTxe2x80x9d hereinafter) to improve the characteristics of the TIGBT shown in FIGS. 7A-7C, where FIG. 8A is an upper plan view thereof and FIGS. 8B and 8C are sectional views taken on lines A-Axe2x80x2 and B-Bxe2x80x2 in FIG. 8A, respectively. This improved TIGBT structure is different from the old TIGBT structure in FIGS. 7A, 7B, and 7C in that an nxe2x88x92-type semiconductor layer (i.e., carrier stored region) 113 for storing carriers is interposed between the p-type base region 104 and the nxe2x88x92-type base layer 103.
The operation of the conventional IGBT will be described below with reference to FIGS. 7A to 7C and FIGS. 8A to 8C. In each of the structures shown in the FIGS. 7A to 7C and FIGS. 8A to 8C, while a predetermined positive collector voltage VCE is applied across the emitter electrode 111 and the collector electrode 112, a predetermined positive gate voltage VGE is applied across the emitter electrode 111 and the trench gate electrode 110 to turn on the gate.
At this time, the type of the channel region is inverted from a p type to an n type to form a channel, and electrons are moved from the emitter electrode 111 and implanted into the nxe2x88x92-type base layer 103. The implanted electrons set the region between the p+-type substrate 101 and the nxe2x88x92-type base layer 103 in a forward bias state. Implantation of carrier holes from the p+-type substrate 101 considerably decreases the resistance of the nxe2x88x92-type base layer 103 and increases the current capacity of the IGBT. In this manner, implantation of holes from the p+-type substrate 101 in the IGBT decreases the resistance of the nxe2x88x92-type semiconductor layer 103.
An operation performed when the IGBT is turned off will be described below. In the structures FIGS. 7A to 7C and FIGS. 8A to 8C, the gate voltage VGE applied across the emitter electrode 111 and the trench gate electrode 110 in the ON state is set to zero or negative (inverted vias) More specifically, when the gate is turned off, the channel region having its conductivity type inverted into an n type is returned to a p-type region, and the implantation of electrons from the emitter electrode 111 into the nxe2x88x92-type base layer 103 is stopped. The stop of implantation of electrons causes the implantation of holes from the p+-type substrate 101 to be stopped. Thereafter, the electrons and holes stored in the nxe2x88x92-type base layer 103 (and the n+-type buffer layer 102) are collected into the collector electrode 112 and the emitter electrode 111, or are combined to each other again to disappear.
The characteristics of the TIGBT shown in FIGS. 7A to 7C can be improved compared to a plane gate IGBT because MOS transistors on the upper surface of the TIGBT can be micropatterned to have a size which is about {fraction (1/10)} the size of the MOS transistors of a plane gate IGBT. In the plane gate IGBT, a current path is formed in a region sandwiched by a p-type base layer on the upper surface, and a voltage drop in this region is large. However, in the above-described TIGBT, the gate 110 is formed to penetrate the p-type base region 104. For this reason, the current path has no region surrounded by the p-type base layer, so that the characteristics can be improved.
In the CSTBT shown in FIGS. 8A to 8C, the nxe2x88x92-type semiconductor layer (carrier stored region) 113 for storing carriers is formed on the lower surface of the p-type base region 104. For this reason, holes from the p+-type substrate 101 are prevented from passing through the emitter electrode 111, and the holes are stored in the carrier stored region 113 located on the lower surface of the p-type base region 104. Therefore, ON voltage can be decreased to a voltage which is lower than that of the TIGBT.
However, in the conventional TIGBT shown in FIGS. 7A to 7C, since the cell size is reduced to a size which is about {fraction (1/10)} the cell size of a plane gate, the ON voltage can be considerably reduced advantageously, but a gate capacity and a short-circuit current increase disadvantageously. In order to solve the problem, the pitches used when the trench gates are formed may be increased to increase the cell size. However, the increase in cell size causes the ON voltage of the TIGBT to increase.
On the other hand, in the CSTBT shown in FIGS. 8A to 8C, an increase in cell size suppresses the ON voltage from increasing, but a withstand voltage decreases disadvantageously. In particular, the decrease in withstand voltage fatally influences a switching element. For this reason, the above problem is not solved by only the increase in cell size.
FIGS. 9 and 10 show results obtained such that dependencies of a change in withstand voltage (FIG. 9) and a change in ON voltage (FIG. 10) when p-type base intervals (trench pitches) W are increased in the TIGBT and the CSTBT are calculated by using device simulation. In this case, the conventional TIGBT and the conventional CSTBT are designed such that the p-type base intervals are set to be 3 xcexcm. In this device simulation, the results are obtained when the trench intervals (p-type base intervals) are changed to 11 xcexcm. When the trench intervals are 11 xcexcm, the cell size is three times a conventional cell size, and the gate capacity is ⅓ compared to a conventional gate capacity.
As is apparent from the simulation calculation results shown in FIGS. 9 and 10, in the TIGBT (indicated by xe2x97xaf), the increase in trench interval does not largely change the withstand voltage as shown in FIG. 9, but the increase in trench interval sharply increases the ON voltage as shown in FIG. 10.
On the other hand, in the CSTBT (indicated by xcex94), the increase in trench interval does not largely change the ON voltage as shown in FIG. 10, the increase in trench interval sharply decreases the withstand voltage as shown in FIG. 9. When the trench interval is 5 xcexcm, the withstand voltage was 200 V or less, and when the trench interval is 6 xcexcm, the withstand voltage is 100 V or less. When the trench interval is 6 xcexcm, the withstand voltage is 100 V or less. When the trench interval is larger than 6 xcexcm, the withstand voltage is almost 0V. As described above, when the trench interval is increased to decrease the gate capacity and the short-circuit current (i.e., the cell size is increased), an increase in ON voltage (in the TIGBT) or a decrease in withstand voltage (in the CSTBT) are caused.
As conventional improved versions of the conventional TIGBT and CSTBT, as shown in FIGS. 11A, 11B, and 11C (TIGBT) and FIGS. 12A, 12B, and 12C (CSTBT), there are devised improved versions of constitutions in which gate electrodes 110 formed in trenches and emitter electrodes 111 are connected to each other without changing pitches at which the trench gates are formed. More specifically, in each of the configurations shown in FIGS. 11A to 11C and FIGS. 12A to 12C, the emitter electrode 111 is connected to the upper surface of the second gate electrode portion 110b. 
Each of these configurations means that the cell of the second gate electrode portion 110b connected to the emitter electrode 111 is a dummy gate region which has a gate voltage VGE of 0 V and which does not function as a gate. Although the TIGBT and the CSTBT have the same sizes as those of the conventional TIGBT and the CSTBT which are shown in FIGS. 7A to 7C and FIGS. 8A to 8C, the TIGBT and the CSTBT advantageously do not cause the withstand voltages to decrease.
On the other hand, power semiconductor elements such as IGBTs or diodes are mounted in one package, and are frequently used in a power conversion device as a power module. At this time, the connection between an electrode of the power module and the power semiconductor element is generally performed by ultrasonic connection using, for example, an aluminum wire or the like. However, the power semiconductor element handles a very high power, and has a limit (power cycle length) at which the joint portion between the aluminum wire and the emitter electrode is finally peeled by a temperature cycle, which is a factor of determining the life of the power module.
Increases of the joint strength and the joint area between the aluminum wire and the emitter electrode are effective to improve the power cycle length. However, in a configuration using the TIGBT and the CSTBT shown in FIGS. 11A to 11C and FIGS. 12A to 12C, a crack extending from the connection region between the emitter electrode 111 and the second gate electrode 110b may be generated to increase a probability that a gate short circuit or a withstand-voltage short circuit occurs disadvantageously. It may be considered as a factor that a stress caused by the ultrasonic connection easily spreads inside the silicon gate electrode because the joint strength is relatively high between the emitter electrode and the second gate electrode being in contact with the emitter electrode.
The present invention has been made to solve the above problems, and has as its object to provide an insulated gate semiconductor device and a method of manufacturing the insulated gate semiconductor device which can control a gate capacity and suppress a short-circuit current in wire bonding connection, and which can maintain a preferable power cycle length.
In order to achieve the above object, in one aspect of the present invention, an insulated gate semiconductor device includes: a semiconductor substrate of a first conductivity type; a collector region of a second conductivity type formed on a lower major surface of the semiconductor substrate; a collector electrode connected to the collector region; a base region of the second conductivity type selectively formed on an upper major surface of the semiconductor substrate; an emitter region of the first conductivity type selectively formed in the base region; and a plurality of trenches including first, second, and third trenches selectively formed in the base region, each of the trenches having a depth passing through the base region and reaching the semiconductor substrate. First, second, and third gate electrodes buried in the first, second, and third trenches through insulating films, respectively, and the base region, emitter region, and second gate electrode are commonly connected to an emitter electrode, wherein the third gate electrode is connected to only the first gate electrode, and the emitter electrode is partially connected to the second gate electrode.
In another aspect of the present invention, a method of manufacturing an insulated gate semiconductor device includes the steps of: forming a collector region of a second conductivity type on a lower major surface of a semiconductor substrate of a first conductivity type; forming a collector electrode connected to a lower major surface of the collector region; selectively forming a base region of the second conductivity type on an upper major surface of the semiconductor substrate; selectively forming an emitter region of the first conductivity type in the base region; and selectively forming a plurality of trenches including first, second, and third trenches in the base region, each of the trenches having a depth passing through the base region and reaching the semiconductor substrate. First, second, and third gate electrodes are buried in the first, second, and third trenches through insulating films, respectively and there is formed an emitter electrode to which upper surface portions of the base region, emitter region and second gate electrode are commonly connected, wherein the third gate electrode is connected to only the first gate electrode, and the second gate electrode is partially connected to the emitter electrode.
According to the present invention, there can be obtained an effect that, when an aluminum wire is connected by an emitter electrode by ultrasonic connection, a portion where a stress directly acts on a polysilicon surface of a gate electrode can be reduced. Therefore, the conventional problem that a crack occurrence from a connection region between an emitter electrode and a second gate electrode can be solved and a gate short circuit and a withstand-voltage short circuit can be effectively suppressed from being generated.